The minimum operational supply voltage (Vccmin) is an important parameter of today's processors. Reducing Vccmin is an important way to reduce the power consumption of a processor. Register files (RF) memory cells, commonly used for cache, inside the processor are the limiting blocks in reducing Vccmin. RF Vccmin is typically the maximum of three components: write Vccmin, read Vccmin, and retention Vccmin.
FIG. 1 shows a conventional, so-called “8T” register file (RF) bit cell having a separate read port for decoupled read operation. Read Vmin is determined by the Local Bit-Line (LBL) evaluation delay and/or LBL noise. Keeper devices p-type transistors, (K1-K3) are used to mitigate the noise impact. Due to contention between pull-down devices (N6, N7) of the read port and those of the keeper devices, the LBL evaluation delay is affected by Vmin, i.e., as Vmin goes down, the LBL delay typically increases.
Unfortunately, with the read port circuit of FIG. 1, the amount to which Vmin may be lowered is limited, e.g., primarily due to the variations in the read port bottom transistor (N7) and increased keeper strength due to width quantization. Accordingly, new approaches may be desired.